1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which an impurity in a conductive silicon film having a prescribed pattern is activated by applying heat to the conductive film.
2. Description of the Background Art
Recently, a channel region of a transistor has been reduced in length with miniaturization of a semiconductor device. As a result, a short channel effect significantly affects transistor characteristics. Therefore, a drain engineering is increasingly important in order to suppress the short channel effect. A technique concerning impurity implantation for forming a LDD (Lightly Doped Drain) structure, an SPI (Shallow Pocket Implant) structure or the like is used as the drain engineering in a semiconductor device.
Furthermore, a conventional buried-channel type transistor cannot attain a sufficient drive capability as a drive voltage becomes smaller with a higher threshold voltage. Therefore, a surface-channel type transistor has been commonly used.
FIGS. 12 and 13 show the steps of manufacturing a semiconductor device including a P type field effect transistor and a resistance element using a polysilicon film doped with a P+ type impurity, as an exemplary step of manufacturing a semiconductor device using the conventional technique described above.
In the conventional method of manufacturing a semiconductor device, through the steps shown in FIGS. 12 and 13, a semiconductor device is formed having an N type well region 101, an element isolation region 102, a P+ type gate electrode 103a, a P+ type resistance element 103b, a P− type impurity diffusion region 104, a sidewall insulating film 105 and a P type impurity diffusion region 106.
In the method of manufacturing a semiconductor device shown in FIGS. 12 and 13, first, N type well region 101 and element isolation region 102 are formed on a semiconductor substrate. Next, polysilicon film 103 which will be gate electrode 103a and resistance element 103b is formed by etching a polysilicon film non-doped or doped with an impurity into a prescribed pattern. Thereafter, in order to form P− type impurity diffusion region 104 to form a part of the LDD structure shown in FIG. 13, boron is implanted into an element formation region using polysilicon film 103 to be gate electrode 103a as a mask. As a result, the structure shown in FIG. 12 results.
Next, sidewall insulating film 105 made of a TEOS (Tetra Ethyle Ortho Silicate) oxide film and the like is formed on the side wall of the polysilicon film to be gate electrode 103a. Thereafter, in order to form P+ type impurity diffusion region 106 having an impurity concentration higher than P− type impurity diffusion region 104, P+ type gate electrode 103a and resistance element 103b of P+ type polysilicon film, a step of implanting an impurity such as boron is performed. Then, a thermal process is performed to activate the respective impurities included in the polysilicon film as P+ type gate electrode 103a and P+ type resistance element 103b and P+ type impurity diffusion region 106. The structure shown in FIG. 13 thereby results.
In the step of performing the thermal process as described above, the surfaces of impurity diffusion region 106 and the polysilicon film to be gate electrode 103a and resistance element 103b are bare, when heat is applied to the respective impurities included in impurity diffusion region 106 and the polysilicon film to be gate electrode 103a and resistance element 103b. Therefore, the respective impurities included in impurity diffusion region 106 and the polysilicon film to be gate electrode 103a and resistance element 103b diffuse outside thereof (out-diffusion).
As a result, the concentrations of the respective impurities included within impurity diffusion region 106, gate electrode 103a and resistance element 103b become low. In other words, the degree of impurity activation is reduced. Consequently, the transistor characteristics are deteriorated, resistance values of resistance elements become higher than desired values, and variations in resistance values of a plurality of resistance elements are increased.
The conventional method of manufacturing a semiconductor device has the following problem in the step of performing a thermal process for activating the impurity within the conductive silicon film having a prescribed pattern to be impurity diffusion region 106, gate electrode 103a and resistance element 103b and the like.
With the conventional method of manufacturing a semiconductor device described above, it is impossible to suppress reduction of the degree of impurity activation in the conductive silicon film having a prescribed pattern resulting from out-diffusion of impurity in the conductive silicon film having a prescribed pattern. Therefore, in a step of forming a pattern for each element, a conductive silicon film having a prescribed pattern having a desired resistance value cannot be formed.
Furthermore, in a semiconductor device in which an absolute value of resistance value of a resistance element is important, the following problem arises.
In forming a resistance element, plural kinds of extra resistance elements presumably having desired resistance values are formed in advance. Then, after prescribed manufacturing steps are once completed, a voltage is applied to a resistance element to be checked if it has a desired resistance value. If a desired resistance value is not obtained, a resistance element that attains a desired resistance value is re-formed using a resistance element selected from plural kinds of extra resistance elements by a trimming technique. This operation, however, requires a great deal of time.
Therefore, in a step of forming a resistance element having a prescribed pattern, it is urgently necessary to reduce the load of re-forming a desired resistance element using the aforementioned trimming technique by forming a resistance element having a desired resistance value.